This invention relates generally to integrated circuits and, more particularly, to integrated circuit MOSFET devices and methods for their manufacture.
Metal oxide semiconductor field effect transistors (MOSFETs) are basic electronic devices commonly used in many integrated circuits (ICs). A typical structure of an n-channel MOSFET is shown in FIG. 1a. A gate structure 10 is formed over a semiconductor substrate 12, and a source 14 and drain 16 region are formed on opposite sides of the gate structure 10 in the semiconductor substrate. The gate structure 10 typically comprises a gate oxide layer 18 and a polysilicon gate layer 20. When a sufficiently high electrical potential is applied to the polysilicon portion gate structure, a shallow conducting region or "channel" C is formed between the source and drain, which permits a current to flow, as indicated by the arrow 21 in FIG. 1a.
The size of individual devices or integrated circuits has decreased over time to permit higher density circuit integration. This decrease in feature size is reflected by a reduction in channel length, i.e., the length of the channel C between the source and the drain of a MOSFET device. A problem known as "hot carrier" or "hot electron" effect arises in devices with channel lengths of 1.2 micron (.mu.) or less. A high electric (E) field develops within the channel and accelerates the carriers (electrons (e.sup.-) for n-channel MOSFETs), some of which may imbed into the gate oxide layer, as illustrated in FIG. 1a. The "hot electron", trapped in the gate oxide layer, can cause an accumulation of charge, which can degrade the transconductance of the device and increase the threshold voltage.
A particular combination of opposing polarity type MOSFETs (i.e. an n-channel and a p-channel MOSFET) in a single device forms a complementary metal oxide semiconductor (CMOS) device. CMOS devices are commonly used due to their very low standby power requirements, which makes them suitable in applications that require low energy consumption. Furthermore, CMOS devices tend to generate less heat than other technologies, so that they are well-suited for high-density circuitry.
FIG. 1b illustrates a standard circuit diagram of a CMOS invertor 23 formed by a p-channel MOSFET (PMOS) 22 and n-channel MOSFET (NMOS) 24. The PMOS transistor 22 acts to pull up the voltage at the output 26 when a low voltage is applied at the input 28. Conversely, the NMOS transistor 24 acts to pull down the output 26 when a high voltage is applied at the input 28.
The CMOS invertor 23 can be damaged by an electrostatic discharge (ESD) event occurring on its output 26. An ESD can occur, for example, when a person who has accumulated a static charge touches the IC of which CMOS invertor 23 is a part.
The degradation due to an ESD event is illustrated in the I-V characteristic curve 30 of FIG. 1c. As shown, a snapback 31 occurs when the ESD voltage exceeds the normal operating voltage, V.sub.n, with permanent damage to an NMOS transistor 24 occurring at point 32 when the device enters second-breakdown. The pull-down transistor 24 of CMOS invertor 23 must therefore be able to withstand an ESD event to ensure a properly functioning circuit.
The production of PMOS and NMOS transistors requires balancing protection against the hot carrier effect and ESD events, since these protections tend to work against each other. Prior art MOSFET structures for combating the hot carrier effect in PMOS and NMOS transistors are illustrated in FIGS. 2a and 2b, respectively. As shown, a PMOS 34 has lightly doped drain (LDD) regions 36, and NMOS 38 has LDD regions 40. These LDD regions reduce the hot carrier effect, as is well known to those skilled in the art.
A variety of processes can be used to produce these structures, but typically, a low-density ion implant of the LDD regions is performed prior to the addition of insulating spacers S along the gate structure sidewalls. After the formation of the spacers, separate higher-density implants are performed for each type of MOSFET to form the source regions, 42 and 44, and drain regions, 46 and 48. An annealing process is then performed to activate the implanted ions. With the provision of the LDD regions, the E field proximate the channel is reduced and therefore the hot carrier effect is decreased, especially in NMOS transistors, which are more susceptible to the hot electron effect. However, the use of LDD NMOS transistors in the output buffer of a device degrades the ESD "hardness", i.e., resistance to static discharge, of the circuit.
A cross-sectional view of an NMOS ESD transistor structure 50 that is formed to combat both problems is shown in FIGS. 2c and 2d. The structure 50 is formed similarly to that described above with the forming of the spacers and implanting of the source and drain regions. However, following the source and drain implants, a heavy-dose phosphorous (i.e. 1-4 E15 atoms/cm.sup.2) implant into the source, 52, and drain, 54, regions of the ESD transistor is performed by first masking all areas except the pull-down (ESD) transistor, then performing the heavy dose implant, and subsequently, removing the mask. The application of a heavy-dose implant overwhelms LDD regions 56, either partially (FIG. 2c) or completely (FIG. 2d).
A problem with this compromise is that the method requires the addition of separate steps of masking, implanting, and mask stripping to achieve the heavy-dose implant, which increases the expense of production. Furthermore, the stripping of the mask after the heavy-dose implant is more difficult and increases the potential contamination and degradation of the device. What is needed is a method for producing the desired structure that is less complicated and less susceptible to contamination and degradation.